Ticket #4087 (closed enhancement: fixed)

Opened 6 weeks ago

Last modified 6 weeks ago

[has-patch] Update verilog syntax highlighting to support latest SystemVerilog standards

Reported by: purdeaandrei Owned by: andrew_b
Priority: minor Milestone: 4.8.25
Component: mcedit Version: master
Keywords: verilog systemverilog syntax Cc:
Blocked By: Blocking:
Branch state: merged Votes for changeset: committed-master

Description

Hello,
I'm going to attach a set of patches to update the Verilog syntax highlighting file to support the latest SystemVerilog? standards.

Attachments

patches.zip (9.6 KB) - added by purdeaandrei 6 weeks ago.
patches

Change History

Changed 6 weeks ago by purdeaandrei

patches

comment:1 Changed 6 weeks ago by andrew_b

  • Owner set to andrew_b
  • Status changed from new to accepted
  • Milestone changed from Future Releases to 4.8.25

comment:2 Changed 6 weeks ago by andrew_b

  • Status changed from accepted to testing
  • Votes for changeset set to committed-master
  • Resolution set to fixed
  • Branch state changed from no branch to merged

Thanks!

Applied as [8d4009134460e7eb3644c06f98649404699134f2].

git log --pretty=oneline e132d7177..8d4009134

comment:3 Changed 6 weeks ago by andrew_b

  • Status changed from testing to closed
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