Ticket #1589 (closed enhancement: fixed)

Opened 15 years ago

Last modified 15 years ago

verilog syntax file

Reported by: arekm Owned by: andrew_b
Priority: minor Milestone: 4.7.0-pre3
Component: mcedit Version: 4.7.0-pre2
Keywords: verilog hdl Cc:
Blocked By: Blocking:
Branch state: Votes for changeset: committed-master

Description

verilog (​http://en.wikipedia.org/wiki/Verilog) syntax file

Attachments

mc-verilog-syntax.patch​ (8.7 KB) - added by arekm 15 years ago.

Change History

Changed 15 years ago by arekm

comment:1 Changed 15 years ago by andrew_b

  • Priority changed from major to minor
  • Component changed from mc-core to mcedit

comment:2 Changed 15 years ago by andrew_b

  • Status changed from new to accepted
  • Owner set to andrew_b
  • severity changed from no branch to on review
  • Milestone changed from 4.7 to 4.7.0-pre3

Thanks!

Created branch 1589_verilog. Parent branch: master.
changeset:06663990f265c30ac0b0497c44b122051f9d4fdc

comment:3 Changed 15 years ago by andrew_b

  • Keywords verilog hdl added

Added missed syntax/Makefile.am
changeset:2dd73e98d957dc5c7c5c329b60668067fc601420 (forced update)

comment:4 Changed 15 years ago by iNode

  • Votes for changeset set to iNode

comment:5 Changed 15 years ago by angel_il

  • Votes for changeset changed from iNode to iNode angel_il
  • severity changed from on review to approved

comment:6 Changed 15 years ago by andrew_b

  • Status changed from accepted to testing
  • Votes for changeset changed from iNode angel_il to commited-master
  • Resolution set to fixed
  • severity changed from approved to merged

Merged to master.
changeset:d3174044bdb7a83de657df891a2975c04c738d2d

comment:7 Changed 15 years ago by andrew_b

  • Status changed from testing to closed
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